This is the home page for our 17th major research exhibit at the IEEE/ACM Supercomputing conference. The exhibit is again under the title Aggregate.Org / University of Kentucky, the informal research consortium led by our KAOS (Compilers, Hardware Architectures, and Operating Systems) group here at the University of Kentucky's Department of Electrical and Computer Engineering. We are booth #1543, appropriately enough located next to NVIDIA.

A Maze Of Twisty Little Passages

Much like last year, the physically big thing in our exhibit this year is a technical demonstration consisting of a large wooden maze with four balls in it. Each of the colored balls has a different path to take (MIMD), yet it is perfectly feasible to get all the balls to their respective destinations by a series of tilts of the table (SIMD). Yes, you really can execute MIMD code on SIMD hardware with good efficiency... Click on the maze above for a ~50MB video showing the maze in action. Fundamentally, this is what our latest software does for GPUs (Graphics Processing Units). Specifically, it can take shared-memory MIMD code written in C and efficiently execute it on an NVIDIA CUDA GPU.

Why do this? GPUs thus far have not had stable, portable, programming support for general-purpose use, so there is virtually no code base for supercomputing applications. Our technology allows codes written for popular cluster and SMP target models to be used directly. New for SC10, we have rewritten the system to make the output of standard MIPS compilers, especially GCC, able to run on GPUs, thus supporting a wide range of fully-featured languages.

The code is VERY ROUGH, but alpha test release version 20101122 is now freely available as source code at http://aggregate.org/MOG/20101122/. There isn't yet any decent documentation, but there is a README and there's a 2009 paper, MIMD Interpretation On A GPU, that explains the concepts quite well.

Living In Stereo

For some years now, we've been quietly working toward improving the quality and capabilities of consumer digital cameras. The more impressive description would be "computational photography" grounded in supercomputer-based analysis and models.... Anyway, we'll be using one of the simplest results throughout our exhibit: anaglyph stereo image capture using a single shot with a single lens; this little trick doesn't even need a computer!

For details, see our Instructable: Use Your Camera To Capture "3D" Anaglyphs

Work Presented

• A Maze Of Twisty Little Passages
  (about the MIMD On GPU -- MOG -- work we have been doing)
• Do-It-Yourself Single-Lens Anaglyph Capture
  (a cheap and easy spin-off of our computational photography work)
• You Can't Always Get What You Want
  (about Line Associative Registers vs. conventional cache)
• One Chip, Millions of Nanocontro9llers
  (about Nanocontrollers - Kentucky Architecture, Nanoprocessors, & Nanocontrollers)
• Powerful Ideas?
  (about predictive power management - Energy Management)
• All Together Now
  (about Aggregate Function Networks -- Theory, Software, and Hardware -- lately, this is mostly about on-chip AFNs for CMPs and software for GPUs)
• Flat Outperformance
  (about Flat Neighborhood Networks - FNN, NetWires)

Some related theses from our group:

• Akshay Vummannagari, Verilog And FPGA Prototype Of A Nanocontroller System (PDF), May, 2010.
• Muthulakshmi Muthukumarasamy, Extraction And Prediction Of System Properties Using Variable-N-Gram Modeling And Compressive Hashing (PDF), 2010.
• Shashi Deepa Arcot, Genetic Algorithm Controlled Common Subexpression Elimination For Spill-Free Register Allocation (PDF), University of Kentucky MSEE Thesis, December, 2009.
• Nien Yi Lim, Separating Instruction Fetches From Memory Accesses: ILAR (Instruction Line Associative Registers) (PDF), November, 2009.
• Diego A. Rivera Polanco, Collective Communication and Barrier Synchronization on NVIDIA CUDA GPUs (PDF), University of Kentucky MSEE Thesis, September, 2009.
• Bobby Dalton Young, MPI Within A GPU (PDF), University of Kentucky MSEE Thesis, http://hdl.handle.net/10225/1085, July, 2009.
• Soohong P. Kim, Chip Multiprocessors with On-Chip Aggregate Function Network, Purdue University PhD Dissertation, (unofficial local PDF copy pending Purdue posting), August, 2009.
• Akil Kaveti, HDL Implementation and Analysis of a Residual Register for a Floating-Point Arithmetic Unit (PDF), University of Kentucky MSEE Thesis, http://hdl.handle.net/10225/893, 2008.
• Sarojini Priyadarshini Rajachidambaram, Kentucky's Adapter for Parallel Execution and Rapid Synchronization , University of Kentucky MS Thesis, http://hdl.handle.net/10225/709, 2007.
• Swetha Mitta, Kentucky's Adapter for Parallel Execution and Rapid Synchronization , University of Kentucky MSEE Thesis, http://hdl.handle.net/10225/621, 2007.
• Chenxing Wang, Dynamic Voltage Scaling for Priority-Driven Scheduled Distributed Real-Time Systems , University of Kentucky PhD Dissertation, http://hdl.handle.net/10225/747, 2007.
• Timothy Ian Mattox, Exploiting Sparseness of Communication Patterns for the Design of Networks in Massively Parallel Supercomputers (PDF), University of Kentucky PhD Dissertation, http://hdl.handle.net/10225/280, 2006.
• Krishna Melarkode, Line Associative Registers (PDF) University of Kentucky MSEE Thesis, http://hdl.handle.net/10225/255, 2004.

Live Camera

The only thing set in stone is our name.